/* ads8308.h - Motorola MPC8308 ADS board header */

/* Copyright 1984-2005 Wind River Systems, Inc. */

/*
modification history
--------------------
01a,10jan05,dtr  adapted from ads827x.h
*/

/*
This file contains I/O addresses and related constants for the
Motorola MPC8349E ADS board.
*/

#ifndef	INCads8308h
#define	INCads8308h

#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */

#define EIEIO_SYNC WRS_ASM (" eieio; sync")

#ifndef  _ASMLANGUAGE
# if (defined(_WRS_VXWORKS_MAJOR) && (_WRS_VXWORKS_MAJOR >= 6))
/* nothing needed */
# else  /* _WRS_VXWORKS_MAJOR */
typedef void * VIRT_ADDR;
typedef void * PHYS_ADDR;
# endif  /* _WRS_VXWORKS_MAJOR */
#endif  /* _ASMLANGUAGE */

#ifndef M8260ABBREVIATIONS
#define M8260ABBREVIATIONS

#ifdef  _ASMLANGUAGE
#define CAST(x)
#else /* _ASMLANGUAGE */
typedef volatile UCHAR VCHAR;   /* shorthand for volatile UCHAR */
typedef volatile INT32 VINT32; /* volatile unsigned word */
typedef volatile INT16 VINT16; /* volatile unsigned halfword */
typedef volatile INT8 VINT8;   /* volatile unsigned byte */
typedef volatile UINT32 VUINT32; /* volatile unsigned word */
typedef volatile UINT16 VUINT16; /* volatile unsigned halfword */
typedef volatile UINT8 VUINT8;   /* volatile unsigned byte */
#define CAST(x) (x)
#endif  /* _ASMLANGUAGE */

#endif /* M8260ABBREVIATIONS */

#undef  CPU
#define CPU	PPC603				/* CPU type */

#define N_SIO_CHANNELS	 	2		/* No. serial I/O channels */

/* define the decrementer input clock frequency */
#define SPD_DATA_SIZE         128
#undef  BOOT_LINE_SIZE
#define BOOT_LINE_SIZE        256
#undef  NV_RAM_SIZE
#define NV_RAM_SIZE           256  
#define NV_RAM_SIZE_WRITEABLE NV_RAM_SIZE  /* force VTS to only use 128 bytes */
#define NV_RAM_READ(x)        sysNvRead (x)
#define NV_RAM_WRITE(x,y)     sysNvWrite (x,y)

/* Base Address of Memory Mapped Registers */
#define CCSBAR_INIT  0xFF400000
#define CCSBAR           0xE0000000
#define CCSBAR_SIZE  0x100000/* 1MB 0x100000*/

/* Register Set Base addresses */
#define PQ2PRO

#define SCCFG_REG_BA           0x00100 
#define WDT_REG_BA             0x00200
#define QUICC_RTC_BASE         0x00300
#define QUICC_PIT_BASE         0x00400
#define QUICC_GTM1_BASE        0x00500
#define QUICC_GTM2_BASE        0x00600
#define SIC_REG_BA             0x00700
#define ARBITER_REG_BA         0x00800
#define RESETM_REG_BA          0x00900

#define CLKM_REG_BA            0x00A00
#define DDR_REG_BA             0x02000
#define LBC_REG_BA             0x05000
#define DMA_REG_BA             0x08100
#define PCICFG_REG_BA          0x08300
#define SEC_REG_BA             0x101B4


#define DMA_NUM 4
/* Define the register definition and interrupt numbers based on 
 * cpu varient */

#include "quiccIntrCtl.h"
#include "quiccLbc.h"

/* system & processor version */


/* System Configuration Control */

#define M83XX_SGPRL(base)  (CAST(VUINT32 *)((base) + SCCFG_REG_BA + 0x00 ))
#define M83XX_SGPRH(base)  (CAST(VUINT32 *)((base) + SCCFG_REG_BA + 0x04 ))
#define M83XX_SPRIDR(base) (CAST(VUINT32 *)((base) + SCCFG_REG_BA + 0x08 ))


#define M83XX_SPCR(base)  (CAST(VUINT32 *)((base) +  SCCFG_REG_BA + 0x10 ))
#define M83XX_SPCR_OPT 0x00800000
#define M83XX_SPCR_TBEN 0x00400000

#define M83XX_SICRL(base)  (CAST(VUINT32 *)((base) + SCCFG_REG_BA + 0x14 ))
#define M83XX_SICRH(base)  (CAST(VUINT32 *)((base) + SCCFG_REG_BA + 0x18 ))



/* Watch Dog Registers */

#define M83XX_SWCRR(base)  (CAST(VUINT32 *)((base) + WDT_REG_BA + 0x04 ))
#define M83XX_SWCNR(base)  (CAST(VUINT32 *)((base) + WDT_REG_BA + 0x08 ))
#define M83XX_SWSRR(base)  (CAST(VUINT16 *)((base) + WDT_REG_BA + 0x0E ))


/* Clock Module */
#define M83XX_SPMR(base)  (CAST(VUINT32 *)((base) + CLKM_REG_BA + 0x00 ))
#define M83XX_SPMR_LBIU_VAL(spmrVal) (spmrVal >> 31);
#define M83XX_SPMR_DDR_VAL(spmrVal) (spmrVal >> 30) & 0x1;
#define M83XX_SPMR_SPMF_VAL(spmrVal) (spmrVal >> 24) & 0xf;
#define M83XX_SPMR_CLK_DIV(spmrVal) (spmrVal >> 23) & 0x1;
#define M83XX_SPMR_CLK_PLL(spmrVal) (spmrVal >> 16) & 0x7f;

#define M83XX_OCCR(base)  (CAST(VUINT32 *)((base) + CLKM_REG_BA + 0x04 ))
#define M83XX_SCCR(base)  (CAST(VUINT32 *)((base) + CLKM_REG_BA + 0x08 ))

#define M83XX_SCCR_RES_MSK      0xf3f10000      /* reserved field Mask */

/* Arbiter registers*/

#define M83XX_ACR(base)   (CAST(VUINT32 *)((base) + ARBITER_REG_BA + 0x00))
#define M83XX_ATR(base)   (CAST(VUINT32 *)((base) + ARBITER_REG_BA + 0x04))
#define M83XX_AER(base)   (CAST(VUINT32 *)((base) + ARBITER_REG_BA + 0x0c))
#define M83XX_AIDR(base)   (CAST(VUINT32 *)((base) + ARBITER_REG_BA + 0x10))
#define M83XX_AMR(base)   (CAST(VUINT32 *)((base) + ARBITER_REG_BA + 0x14))
#define M83XX_AEATR(base)   (CAST(VUINT32 *)((base) + ARBITER_REG_BA + 0x18))
#define M83XX_AEADR(base)   (CAST(VUINT32 *)((base) + ARBITER_REG_BA + 0x1c))
#define M83XX_AERR(base)   (CAST(VUINT32 *)((base) + ARBITER_REG_BA + 0x20))

/* Reset Configuration Module */

#define M83XX_RCWLR(base)   (CAST(VUINT32 *)((base) + RESETM_REG_BA + 0x00))
#define M83XX_RCWHR(base)   (CAST(VUINT32 *)((base) + RESETM_REG_BA + 0x04))
#define M83XX_RSR(base)     (CAST(VUINT32 *)((base) + RESETM_REG_BA + 0x10))
#define M83XX_RMR(base)   (CAST(VUINT32 *)((base) + RESETM_REG_BA + 0x14))
#define M83XX_RPR(base)   (CAST(VUINT32 *)((base) + RESETM_REG_BA + 0x18))
#define M83XX_RCR(base)   (CAST(VUINT32 *)((base) + RESETM_REG_BA + 0x1c))
#define M83XX_RCER(base)   (CAST(VUINT32 *)((base) + RESETM_REG_BA + 0x20))


/* I2C1 Controller */

#define  M8308_I2C1_BASE                 0x03000 

#define  I2C1ADR    0x03000
#define  I2C1FDR    0x03004
#define  I2C1ICR    0x03008
#define  I2C1ISR    0x0300c
#define  I2C1IDR    0x03010
#define  I2C1DFSRR  0x03014

#define  M8308_I2C1ADR(base)            (CAST(VUINT8 *)((base) | I2C1ADR))
#define  M8308_I2C1FDR(base)            (CAST(VUINT8 *)((base) | I2C1FDR))
#define  M8308_I2C1ICR(base)            (CAST(VUINT8 *)((base) | I2C1ICR))
#define  M8308_I2C1ISR(base)            (CAST(VUINT8 *)((base) | I2C1ISR))
#define  M8308_I2C1IDR(base)            (CAST(VUINT8 *)((base) | I2C1IDR))
#define  M8308_I2C1DFSRR(base)          (CAST(VUINT32 *)((base) | I2C1DFSRR))


/* I2C2 Controller */

#define  M8308_I2C2_BASE                 0x03100 

#define  I2C2ADR    0x03100
#define  I2C2FDR    0x03104
#define  I2C2ICR    0x03108
#define  I2C2ISR    0x0310c
#define  I2C2IDR    0x03110
#define  I2C2DFSRR  0x03114

#define  M8308_I2C2ADR(base)            (CAST(VUINT8 *)((base) | I2C2ADR))
#define  M8308_I2C2FDR(base)            (CAST(VUINT8 *)((base) | I2C2FDR))
#define  M8308_I2C2ICR(base)            (CAST(VUINT8 *)((base) | I2C2ICR))
#define  M8308_I2C2ISR(base)            (CAST(VUINT8 *)((base) | I2C2ISR))
#define  M8308_I2C2IDR(base)            (CAST(VUINT8 *)((base) | I2C2IDR))
#define  M8308_I2C2DFSRR(base)          (CAST(VUINT32 *)((base) | I2C2DFSRR))


/* Security IMMR registers */
#define QUICC_SECBR(base) (CAST(VUINT32 *)((base) + SEC_REG_BA + 0x0)) 
#define QUICC_SECMR(base) (CAST(VUINT32 *)((base) + SEC_REG_BA + 0x4))

#define SEC_ENG_BASE_ADRS (CCSBAR + 0x40000)
#define SEC_ENG_SIZE      0x20000
#define SEC_ENG_SIZE_MASK 0xfffe0000

/* Local address windows */

#define M83XX_LBLAWBARn(base,n)      \
	   (CAST(VUINT32 *)((base) + 0x20 + (n*0x8)))

#define M83XX_LBLAWARn(base,n)      \
	   (CAST(VUINT32 *)((base) + 0x24 + (n*0x8)))

#define M83XX_PCILAWBARn(base,n)      \
	   (CAST(VUINT32 *)((base) + 0x60 + (n*0x8)))

#define M83XX_PCILAWARn(base,n)      \
	   (CAST(VUINT32 *)((base) + 0x64 + (n*0x8)))

#define M83XX_PCIELAWBARn(base,n)      \
	   (CAST(VUINT32 *)((base) + 0x80 + (n*0x8)))

#define M83XX_PCIELAWARn(base,n)      \
	   (CAST(VUINT32 *)((base) + 0x84 + (n*0x8)))

#define M83XX_DDRLAWBARn(base,n)      \
	   (CAST(VUINT32 *)((base) + 0xA0 + (n*0x8)))

#define M83XX_DDRLAWARn(base,n)      \
	   (CAST(VUINT32 *)((base) + 0xA4 + (n*0x8)))

#define LAWBAR_ADRS_SHIFT  0

#define  LAWAR_ENABLE       0x80000000
/* LAWAR SIZE Settings */ 
#define  LAWAR_SIZE_4KB     0x0000000B
#define  LAWAR_SIZE_8KB     0x0000000C
#define  LAWAR_SIZE_16KB    0x0000000D
#define  LAWAR_SIZE_32KB    0x0000000E
#define  LAWAR_SIZE_64KB    0x0000000F
#define  LAWAR_SIZE_128KB   0x00000010
#define  LAWAR_SIZE_256KB   0x00000011
#define  LAWAR_SIZE_512KB   0x00000012
#define  LAWAR_SIZE_1MB     0x00000013
#define  LAWAR_SIZE_2MB     0x00000014
#define  LAWAR_SIZE_4MB     0x00000015
#define  LAWAR_SIZE_8MB     0x00000016
#define  LAWAR_SIZE_16MB    0x00000017
#define  LAWAR_SIZE_32MB    0x00000018
#define  LAWAR_SIZE_64MB    0x00000019
#define  LAWAR_SIZE_128MB   0x0000001A
#define  LAWAR_SIZE_256MB   0x0000001B
#define  LAWAR_SIZE_512MB   0x0000001C
#define  LAWAR_SIZE_1GB     0x0000001D
#define  LAWAR_SIZE_2GB     0x0000001E

/* PCI Window SIZE  */ 
#define  PCI_SIZE_4KB     0x0000000B
#define  PCI_SIZE_8KB     0x0000000C
#define  PCI_SIZE_16KB    0x0000000D
#define  PCI_SIZE_32KB    0x0000000E
#define  PCI_SIZE_64KB    0x0000000F
#define  PCI_SIZE_128KB   0x00000010
#define  PCI_SIZE_256KB   0x00000011
#define  PCI_SIZE_512KB   0x00000012
#define  PCI_SIZE_1MB     0x00000013
#define  PCI_SIZE_2MB     0x00000014
#define  PCI_SIZE_4MB     0x00000015
#define  PCI_SIZE_8MB     0x00000016
#define  PCI_SIZE_16MB    0x00000017
#define  PCI_SIZE_32MB    0x00000018
#define  PCI_SIZE_64MB    0x00000019
#define  PCI_SIZE_128MB   0x0000001A
#define  PCI_SIZE_256MB   0x0000001B
#define  PCI_SIZE_512MB   0x0000001C
#define  PCI_SIZE_1GB     0x0000001D
#define  PCI_SIZE_2GB     0x0000001E


/* Offsets for DDR registers */
#define DDRBA      (CCSBAR | DDR_REG_BA)
#define CS0_BNDS   0x000
#define CS1_BNDS   0x008
#define CS2_BNDS   0x010
#define CS3_BNDS   0x018
#define CS0_CONFIG 0x080
#define CS1_CONFIG 0x084
#define CS2_CONFIG 0x088
#define CS3_CONFIG 0x08C

#define TIMING_CFG_1 0x108
#define TIMING_CFG_2 0x10C
#define DDR_SDRAM_CFG 0x110
#define DDR_SDRAM_MODE_CFG 0x118
#define DDR_SDRAM_INTERVAL 0x124
#define DDR_SDRAM_CLK_CNTRL 0x130

#define DDR_DATA_ERR_INJECT_HI 0xe00
#define DDR_DATA_ERR_INJECT_LO 0xe04
#define DDR_ECC_ERR_INJECT 0xe08
#define DDR_CAPTURE_DATA_HI 0xe20
#define DDR_CAPTURE_DATA_LO 0xe24
#define DDR_CAPTURE_ECC 0xe28
#define DDR_ERR_DETECT 0xe40
#define DDR_ERR_DISABLE 0xe44
#define DDR_ERR_INT_EN 0xe48
#define DDR_CAPTURE_ATTRIBUTES 0xe4c
#define DDR_CAPTURE_ADDRESS 0xe50
#define DDR_ERR_SBE 0xe58

/* add PCI access macros */
#define PCI_MEMIO2LOCAL(x) \
         (((UINT32)x  - PCI_MEMIO_ADRS) + CPU_PCI_MEMIO_ADRS)     
/* PCI IO memory adrs to CPU (60x bus) adrs */
       
#define PCI_IO2LOCAL(x) \
     (((UINT32)x  - PCI_IO_ADRS) + CPU_PCI_IO_ADRS)
	     
#define PCI_MEM2LOCAL(x) \
         (((UINT32)x  - PCI_MEM_ADRS) + CPU_PCI_MEM_ADRS)

/* 60x bus adrs to PCI (non-prefetchable) memory address */
	      
#define LOCAL2PCI_MEMIO(x) \
     ((int)(x) + PCI_MSTR_MEM_BUS)


/* PCI defines begin */


/* configuration space reg and int ack */

#define PCI_CFG_ADR_REG        (CCSBAR + PCICFG_REG_BA + 0x00)    
#define PCI_CFG_DATA_REG       (CCSBAR + PCICFG_REG_BA + 0x04)
#define PCI_INT_ACK            (CCSBAR + PCICFG_REG_BA + 0x08)

#define PCI_AUTO_CONFIG_ADRS  0x4c00

#define PPCACR_PRKM_MASK 0XF0
#define PCI_REQUEST_LEVEL 0x3

#define CLASS_OFFSET      0xB
#define CLASS_WIDTH       0x1
#define BRIDGE_CLASS_TYPE 0x6


#define PCICMD_ADRS     (PCI_CFG_BASE + 0x04)  /* PCI cmd reg */
#define PCICMD_VAL      0x00000006             /* PCI COMMAND Default value */
#define PCISTAT_ADRS    (PCI_CFG_BASE + 0x06)  /* PCI status reg */

#define NUM_PCI_SLOTS           0x4            /* 3 PCI slots: 0 to 2 */

#define PCI_XINT1_LVL           0x0            /* PCI XINT1 routed to IRQ0  */
#define PCI_XINT2_LVL           0x1            /* PCI XINT2 routed to IRQ1 */
#define PCI_XINT3_LVL           0x2            /* PCI XINT3 routed to IRQ2 */
#define PCI_XINT4_LVL           0x3            /* PCI XINT3 routed to IRQ2 */

#ifdef ADS_BOARD_REVA
#define PCI_SLOT1_DEVNO        0x12            /* PCI SLOT 1 Device no */
#else
#define PCI_SLOT1_DEVNO        0x0C            /* PCI SLOT 1 Device no */
#endif

#define PCI_LAT_TIMER          0x40            /* latency timer value, 64 PCI clocks */

#define PCI1_DEV_ID      0x826010E3
#define PCI2_DEV_ID      0x826110E3
#define PCI3_DEV_ID      0x826210E3
#define PCI_DEV_ID_82XX  0x00031057  /* Id for MPC8266ADS-PCI board - Rev1 */
#define PCI_DEV_ID_85XX  0x00091057  /* Id for MPC85xxADS-PCI board - Rev2 */
#define PCI_ID_I82559           0x12298086     /* Id for Intel 82559 */
#define PCI_ID_I82559ER         0x12098086     /* Id for Intel 82559 ER */

#define MPC8266ADS_PCI_IRQ       INUM_PCI1

#define PCI_INTA_IRQ     MPC8266ADS_PCI_IRQ
#define PCI_INTB_IRQ     MPC8266ADS_PCI_IRQ
#define PCI_INTC_IRQ     MPC8266ADS_PCI_IRQ
#define PCI_INTD_IRQ     MPC8266ADS_PCI_IRQ

#define DELTA(a,b)		(sysAbs((int)a - (int)b))

#define BUS	0				/* bus-less board */

/* Board Status and Control Registers - unique to ADS */
	     /* Chip Select 1 for 8349E board */

#define	BCSR_BASE_ADRS	0xF8000000		/* BCSR base address */
#define BCSRS_SIZE      0x00008000  		/* 32K of address space */
#define BCSRS_MASK      ~(BCSRS_SIZE - 1)	/* set 32K mask for BCSRs */

#ifdef _ASMLANGUAGE

#define BCSR0		BCSR_BASE_ADRS 	       	/* Register 0 */
#define BCSR1		BCSR_BASE_ADRS + 0x01	/* Register 1 */
#define BCSR2		BCSR_BASE_ADRS + 0x02	/* Register 2 */
#define BCSR3		BCSR_BASE_ADRS + 0x03	/* Register 3 */
#define BCSR4		BCSR_BASE_ADRS + 0x04	/* Register 4 */
#define BCSR5		BCSR_BASE_ADRS + 0x05	/* Register 5 */
#define BCSR6		BCSR_BASE_ADRS + 0x06	/* Register 6 */
#define BCSR7		BCSR_BASE_ADRS + 0x07	/* Register 7 */
#define BCSR8		BCSR_BASE_ADRS + 0x08	/* Register 8 */
#define BCSR9		BCSR_BASE_ADRS + 0x09	/* Register 9 */
#define BCSR10		BCSR_BASE_ADRS + 0x0a	/* Register 10 */
#define BCSR11		BCSR_BASE_ADRS + 0x0b	/* Register 11 */

#else

#define BCSR0   ((uint8_t *)BCSR_BASE_ADRS)	/* Register 0 */
#define BCSR1   (((uint8_t *)BCSR_BASE_ADRS) + 0x01)	/* Register 1 */
#define BCSR2   (((uint8_t *)BCSR_BASE_ADRS) + 0x02)	/* Register 2 */
#define BCSR3   (((uint8_t *)BCSR_BASE_ADRS) + 0x03)	/* Register 3 */
#define BCSR4   (((uint8_t *)BCSR_BASE_ADRS) + 0x04)	/* Register 4 */
#define BCSR5   (((uint8_t *)BCSR_BASE_ADRS) + 0x05)	/* Register 5 */
#define BCSR6   (((uint8_t *)BCSR_BASE_ADRS) + 0x06)	/* Register 6 */
#define BCSR7   (((uint8_t *)BCSR_BASE_ADRS) + 0x07)	/* Register 7 */
#define BCSR8   (((uint8_t *)BCSR_BASE_ADRS) + 0x08)	/* Register 8 */
#define BCSR9   (((uint8_t *)BCSR_BASE_ADRS) + 0x09)	/* Register 9 */
#define BCSR10  (((uint8_t *)BCSR_BASE_ADRS) + 0x0a)	/* Register 10 */
#define BCSR11  (((uint8_t *)BCSR_BASE_ADRS) + 0x0b)	/* Register 11 */


typedef union ads_bcsr 
    {
    struct 
	{
	/* 0 */
	UINT8  geth0_en:1;
	UINT8  geth1_en:1;
	UINT8  geth_rst:1; 
	UINT8  rs232_en:1;
	UINT8  bootwp:1;
	UINT8  led0:1;
	UINT8  led1:1;
	UINT8  spare1:1;
	/* 1 */

	UINT8  cfgClkinDiv:1;
	UINT8  cfgRs:3;
	UINT8  romloc:3;
	UINT8  flashPrt:1;
	/* 2 */

	UINT8  spmf:4;
	UINT8  svCod:2;
	UINT8  bootSeq:2;
	/* 3 */

	UINT8  corePll:7;
	UINT8  swen:1;
	/* 4 */

	UINT8  pciHost:1;
	UINT8  pci64:1;
	UINT8  pci1Arb:1;
	UINT8  pci2Arb:1;
	UINT8  coreDis:1;
	UINT8  bms:1;
	UINT8  lbiucm:1;
	UINT8  ddrcm:1;
	/* 5 */

	UINT8  tsec1m:2;
	UINT8  tsec2m:2;
	UINT8  tsec1MstM:1;
	UINT8  tsec2MstM:1;
	UINT8  spare2:2;
	/* 6 */

	UINT8  testSelect:1;
	UINT8  tpr:1;
	UINT8  tle:1;
	UINT8  lale:1;
	UINT8  jtag2sel:1;
	UINT8  spare3:3;

	} field;
    UINT32 bcsr[7];
    } BCSR_REG;

#endif	/* _ASMLANGUAGE */

#define BCSR0_GETH0_EN    0x80
#define BCSR0_GETH1_EN    0x40
#define BCSR0_GETH_RST    0x20
#define BCSR0_RS232_EN    0x10
#define BCSR0_BOOTWP      0x08 /* protect is low */
#define BCSR0_SIGNAL0     0x04
#define BCSR0_SIGNAL1     0x02
#define BCSR0_SPARE       0x01

#define BCSR1_FLASH_PRT   0x01
#define BCSR0_LED_ON       0
#define BCSR0_LED_OFF      1

/* CPU type in the PVR */

#define CPU_TYPE_8260			0xAAAA		/* value for PPC8260 */
#define CPU_TYPE_8266			0xBBBB		/* value for PPC8266 */
#define	CPU_REV_A1_MASK_NUM		0x0010		/* revision mask num */
#define HIP4_ID			       	0x80810000  /* device ID via PVR */
#define HIP4_MASK	       		0xFFFF0000  /* mask upper word   */
#define HIP7_ID				0x80820000

    /* Default Values */
#define SPCR_DEFAULT_VAL                0x13020000 
#define SICRL_DEFAULT_VAL               0x80000000 
#define SICRH_DEFAULT_VAL               0x00000003 
#if 0
/* 33MHz PCI */
/* Must also flip CLKIN_DIV dip switch on board to 1 */
#define OCCR_DEFAULT_VAL                0xffff0003
#else
/* 66MHz PCI */
/* Must also flip CLKIN_DIV dip switch on board to 0 */
#define OCCR_DEFAULT_VAL                0xff000000
#endif
#define ATR_DEFAULT_VAL                 0x00ff00ff
#define AIDR_DEFAULT_VAL                0x0000003f
#define AERR_DEFAULT_VAL                0x00000000
#define AMR_DEFAULT_VAL                 0x00000007
#define ACR_DEFAULT_VAL                 0x00100000
#define AER_DEFAULT_VAL                 0x0000003f

/* romInit initialization values... */

/* Values for local bus windows before flash is remapped at powerup. */

#define LBLAWBAR0_BOOT_VAL              0x00000000       
/* 2 GB */
#define LBLAWAR0_BOOT_VAL               (LAWAR_ENABLE|LAWAR_SZ_2GB)

#define LBLAWBAR1_BOOT_VAL              0x80000000
/* 2 GB */
#define LBLAWAR1_BOOT_VAL               (LAWAR_ENABLE|LAWAR_SZ_2GB)

#define LBLAWBAR2_BOOT_VAL              0x00000000
#define LBLAWAR2_BOOT_VAL               0x00000000

#define LBLAWBAR3_BOOT_VAL              0x00000000
#define LBLAWAR3_BOOT_VAL               0x00000000

#define BR0_DEFAULT_VAL                 (ROM_BASE_ADRS|0x1001)
/*
For SRAM:
#define OR0_DEFAULT_VAL                 0xff806fa0
*/
/* I also think this needs to be fixed for flash for machine check to work -
   will check on a flash ready board. */
#define OR0_DEFAULT_VAL                 0xff806ff7

#define LBLAWBAR0_DEFAULT_VAL           ROM_BASE_ADRS
/* 8MB */
#define LBLAWAR0_DEFAULT_VAL            (LAWAR_ENABLE|LAWAR_SZ_8MB)

#define LBLAWBAR1_DEFAULT_VAL           BCSR_BASE_ADRS 
#define LBLAWAR1_DEFAULT_VAL            (LAWAR_ENABLE|LAWAR_SZ_8KB)

#define PCILAWBAR0_DEFAULT_VAL          0x80000000
/* 256 MB */
#define PCILAWAR0_DEFAULT_VAL           0x8000001b

#define PCILAWBAR1_DEFAULT_VAL          0x90000000
/* 256 MB */
#define PCILAWAR1_DEFAULT_VAL           0x8000001b

#define BR1_DEFAULT_VAL                 (BCSR_BASE_ADRS|0x801)
#define OR1_DEFAULT_VAL                 0xffffe8f0


/* Hard Reset Configuration Words */
/* Low Word */
/*Byte 0*/
#define HRCW_LOW_LBIU_DIV2   0x80
#define HRCW_LOW_DDR_DIV2    0x40
#define HRCW_LOW_SPMF        0x0f

/* Byte 1*/
#define HRCW_LOW_CORE_PLL   0xFF

/* byte 2 and 3 must be cleared */

/* High Word */
/*Byte 0*/
#define HRCW_HIGH_PCI_HOST     0x80 
#define HRCW_HIGH_PCI64        0x40
#define HRCW_HIGH_PCI1_ARB     0x20
#define HRCW_HIGH_PCI2_ARB     0x10
#define HRCW_HIGH_CORE_DIS     0x08
#define HRCW_HIGH_BMS_HIGH     0x04
#define HRCW_HIGH_BOOT_SEQ_I2C 0x01
#define HRCW_HIGH_BOOT_SEQ_EXT_I2C 0x02

/*Byte 1*/
#define HRCW_HIGH_SWEN         0x80
#define HRCW_HIGH_ROMLOC       0x70
#define ROMLOC_DDR        0x00
#define ROMLOC_PCI1       0x10
#define ROMLOC_PCI2       0x20
#define ROMLOC_GPCM_8BIT  0x50
#define ROMLOC_GPCM_16BIT 0x60
#define ROMLOC_GPCM_32BIT 0x70


/*Byte 2*/
#define HRCW_HIGH_TSEC1M       0xc0
#define HRCW_HIGH_TSEC2M       0x30

#define HRCW_HIGH_TSEC12M_GMII 0xa0

/*Byte 3*/
#define HRCW_HIGH_TLE          0x40


#ifndef _ASMLANGUAGE

/* function declarations */
extern uint32_t sysBaudClkFreq(void);
extern void   sysMsDelay(uint32_t);
extern void   sysDelay(void);
extern uint32_t sysAbs(int);
extern uint32_t sysDecGet(void);
extern UINT32 vxHid2Get();
extern void   vxHid2Set(UINT32);
extern UINT32 vxSvrGet();
#endif /* _ASMLANGUAGE */

#ifdef __cplusplus
}
#endif /* __cplusplus */

#endif /* INCads827xh */
